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w WM8595 24-bit 192khz 2vrms multi-channel codec wolfson microelectronics plc t o receive regular email updates, sign up at http://www.wolfsonmicro.com/enews production data, january 2011, rev 4.2 copyright ? 2011 wolfson microelectronics plc description the WM8595 is a high performance multi-channel audio codec with flexible input/output selection and digital and analogue volume control. features include a 24-bit stereo adc with digital gain control, two 24-bit dacs with independent volume control and clocking, and a range of input/output channel selection options with analogue volume control for flexible routing within current and future audio systems. the WM8595 has a six stereo input selector which accepts input levels up to 2vrms. one stereo input can be selected through an input mux to be routed through to the adc. the WM8595 outputs two stereo audio channels at line levels up to 2vrms, driven from independent dacs. the dac channels include independent digital volume control, and both stereo output channels include analogue volume control with soft ramp. the WM8595 supports up to 2vrms analogue inputs, 2vrms outputs, with sample rates from 32khz to 192khz on the dacs, and 32khz to 96khz on the adc. the WM8595 is controlled via a serial interface with support for 2-wire and 3-wire control with full readback. control of mute, emergency shutdown and reset can also be achieved by pin selection. the WM8595 is ideal for audio applications requiring high performance and flexible routing options, including flat panel digital tv and dvd recorder. the WM8595 is available in a 48-pin qfn package. features ? multi-channel codec with 6 stereo input selector and 2 stereo output selector ? 4-channel dac, 2-channel adc ? 6x2vrms stereo input selector to adc ? 2x2vrms stereo output ? audio performance - dac: 100db snr typical (?a? weighted @ 48khz) - dac: -87db thd typical - adc: 96db snr typical (?a? weighted @ 48khz) - adc: -80db thd typical ? independent sampling rate for adc and dacs possible ? dacs sampling frequency 32khz ? 192khz ? adc sampling frequency 32khz ? 96khz ? dac digital volume control +12db to -100db in 0.5db steps ? adc digital volume control from +30db to -97db in 0.5db steps ? adc input analogue boost control, selectable from 0db, +3db, +6db and +12db ? output analogue volume control +6db to -73.5db in 0.5db steps with zero cross or soft ramp to prevent pops and clicks ? digital multiplexer to interface to multiple digital sources ? dsp, hdmi, memory card ? 2-wire and 3-wire serial control interface with readback and hardware reset, mute and emergency shutdown pins ? adc features master or slave clocking modes ? programmable format audio data interface modes - i2s, lj, rj, dsp ? 3.3v / 9v analogue, 3.3v digital supply operation ? 48-pin qfn package applications ? digital flat panel tv ? dvd-rw ? set top boxes
WM8595 production data w pd, rev 4.2, january 2011 2 block diagram sclk sda cifmode shutdown dgnd dvdd agnd2 avdd2 agnd1 avdd1 adcvmid vref1c vref1gnd vmid2c vref2vdd vref2gnd adc input mux cs adcdat lrclk2 bclk2 mclk2 dacdat2 lrclk1 bclk1 mclk1 dacdat1 mute reset
production data WM8595 w pd, rev 4.2, january 2011 3 table of contents description ....................................................................................................... 1 features............................................................................................................. 1 applications ..................................................................................................... 1 block diagram ................................................................................................. 2 pin configuration ........................................................................................... 4 pin description ................................................................................................ 5 absolute maximum ratings ......................................................................... 6 recommended operating conditions ..................................................... 7 supply current consumption ................................................................... 7 electrical characteristics ...................................................................... 8 terminology .......................................................................................................... 10 master clock timing ........................................................................................... 11 reset timing ........................................................................................................... 11 digital audio interface timing ? slave mode ............................................. 12 digital audio interface timing ? master mode .......................................... 13 control interface timing ? 2-wire mode .................................................... 14 control interface timing ? 3-wire mode .................................................... 15 power on reset (por) ........................................................................................ 16 device description ....................................................................................... 17 introduction ......................................................................................................... 17 control interface .............................................................................................. 18 2-wire (sm-bus compatible) serial control interface mode .............. 18 3-wire (spi compatible) serial control interface mode ...................... 20 digital audio data formats ............................................................................. 21 digital audio interface ..................................................................................... 26 digital audio data sampling rates ................................................................ 28 dac features ......................................................................................................... 29 analogue output volume control ............................................................... 32 adc features ......................................................................................................... 36 digital routing control ................................................................................... 40 pop and click performance ............................................................................ 46 global enable control ..................................................................................... 48 emergency power down ................................................................................... 49 register map ................................................................................................... 50 digital filter characteristics ............................................................... 74 applications information ......................................................................... 78 recommended external components .......................................................... 78 recommended analogue low pass filter .................................................. 79 relevant application notes ............................................................................ 79 package dimensions .................................................................................... 80 important notice .......................................................................................... 81 address ................................................................................................................... 81 revision history ............................................................................................ 82
WM8595 production data w pd, rev 4.2, january 2011 4 pin configuration lineout2l lineout2r agnd2 shutdown mute reset in1l gpio2 gpio1 cs sclk lineout1l lineout1r agnd1 avdd1 sda sdout cifmode vref2vdd vmid1c vmid2c vref2gnd vref1gnd avdd2 ordering information order code temperature range package moisture sensitivity level package body temperature WM8595gefl/v -40 c to +85 c 48-lead qfn (pb-free) msl3 260 o c WM8595gefl/rv -40 c to +85 c 48-lead qfn (pb-free, tape and reel) msl3 260 o c note: reel quantity = 2200
production data WM8595 w pd, rev 4.2, january 2011 5 pin description pin name type description 1 mclk1 digital input/output audio interface port 1 master clock input/output 2 lrclk1 digital input/output audio interface port 1 left/right clock input/output 3 n/c no internal connection 4 bclk1 digital input/output audio interface port 1 bit clock input/output 5 dacdat1 digital input audio interface port 1 data input for dac1 6 mclk2 digital input/output audio interface port 2 master clock input/output 7 lrclk2 digital input/output audio interface port 2 left/right clock input/output 8 bclk2 digital input/output audio interface port 2 bit clock input/output 9 dacdat2 digital input audio interface port 2 data input for dac2 10 adcdat digital output audio interface port 3 data output for adc 11 dvdd supply digital supply 12 dgnd supply digital ground 13 gpio1 digital input/output general purpose input/output 1 14 gpio2 digital input/output general purpose input/output 2 15 shutdown digital i nput emergency shutdown 16 mute digital input hardware dac mute 17 reset digital i nput hardware reset 18 avdd2 supply analogue 9v supply 19 agnd2 supply analogue 9v ground 20 lineout2r analogue output output channel 2 right 21 lineout2l analogue output output channel 2 left 22 lineout1r analogue output output channel 1 right 23 lineout1l analogue output output channel 1 left 24 in1l analogue input input channel 1 left 25 in1r analogue input input channel 1 right 26 in2l analogue input input channel 2 left 27 in2r analogue input input channel 2 right 28 in3l analogue input input channel 3 left 29 in3r analogue input input channel 3 right 30 in4l analogue input input channel 4 left 31 in4r analogue input input channel 4 right 32 in5l analogue input input channel 5 left 33 in5r analogue input input channel 5 right 34 in6l analogue input input channel 6 left 35 in6r analogue input input channel 6 right 36 vref1c analogue output positive reference for adc 37 vmid1c analogue output midrail divider decoupling pin for adc 38 vref1gnd analogue input ground reference for adc 39 vref2vdd analogue input positive reference for dacs 40 vmid2c analogue output midrail divider decoupling pin for dacs 41 vref2gnd analogue input ground reference for dacs 42 avdd1 supply analogue 3.3v supply 43 agnd1 supply analogue 3.3v ground 44 cifmode digital input 2-wire/3-wire mode select 45 sdout digital output serial data output for 3-wire readback 46 cs digital input 3-wire serial control interface latch 47 sclk digital input software mode: serial control interface clock signal 48 sda digital input software mode: bi-directional serial control interface data signal
WM8595 production data w pd, rev 4.2, january 2011 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std-020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specified in ordering information. condition min max digital supply voltage, dvdd -0.3v +4.5v analogue supply voltage, avdd1 -0.3v +7v analogue supply voltage, avdd2 -0.3v +15v voltage range digital inputs dgnd -0.3v dvdd + 0.3v voltage range analogue inputs agnd ? 2.4v avdd1 + 2.4v master clock frequency 38.462mhz ambient temperature (supplies applied) -55 c +125 c storage temperature -65 c +150 c pb free package body temperature (reflow 10 seconds) +260 c package body temperature (soldering 2 minutes) +183 c note: 1. analogue and digital grounds must always be within 0.3v of each other. thermal performance parameter symbol test conditions min typ max unit thermal resistance ? junction to ambient r ja tbd c/w thermal resistance ? junction to case r jc tbd c/w notes: 1. figures given for package mounted on 4-layer fr4 according to jesd51-7. (no forced air flow is assumed). 2. thermal performance figures are estimated.
production data WM8595 w pd, rev 4.2, january 2011 7 recommended operating conditions parameter symbol test conditions min typ max unit digital power supply dvdd 2.97 3.3 3.6 v analogue power supply avdd1 2.97 3.3 3.6 v analogue power supply avdd2 8.1 9 9.9 v ground dgnd/agnd1/ agnd2 0 v operating temperature range t a -40 +85 c notes: 1. digital supply (dvdd) must never be more than 0.3v greater than avdd1 in normal operation. 2. digital ground (dgnd) and analogue grounds (agnd1, agnd2) must never be more than 0.3v apart. supply current consumption test conditions avdd2=9v, avdd1=dvdd=3.3v, agnd1=agnd2=0v, dgnd=0v, t a =+25 ? c, fs=48khz, mclk=256fs unless otherwise stated parameter symbol test conditions min typ max unit adc record (dacs disabled) digital supply current i dvdd fs=48khz, 256fs quiescent 8.6 ma analogue supply 1 current i avdd1 9.2 ma analogue supply 2 current i avdd2 0.01 ma dac playback (adc disabled, one dac disabled) digital supply current i dvdd fs=48khz, 256fs quiescent 5.5 ma analogue supply 1 current i avdd1 6.5 ma analogue supply 2 current i avdd2 2.0 ma digital supply current i dvdd fs=96khz, 256fs quiescent 9.5 ma analogue supply 1 current i avdd1 7.0 ma analogue supply 2 current i avdd2 2.0 ma digital supply current i dvdd fs=192khz, 256fs quiescent 10.0 ma analogue supply 1 current i avdd1 7.0 ma analogue supply 2 current i avdd2 2.0 ma adc record, dac playback (all circuit blocks enabled) digital supply current i dvdd fs=48khz, 256fs quiescent 17.0 ma analogue supply 1 current i avdd1 20.0 ma analogue supply 2 current i avdd2 11.0 ma
WM8595 production data w pd, rev 4.2, january 2011 8 electrical characteristics test conditions avdd2=9v, avdd1=dvdd=3.3v, agnd1=agnd2=0v, dgnd=0v, t a =+25 ? c, 1khz signal, fs=48khz, mclk=256fs unless otherwise stated parameter symbol test conditions min typ max unit digital logic levels input low level v il 0.3xdvdd v input high level v ih 0.7xdvdd v output low level v ol 0.1 x dvdd v output high level v oh 0.9 x dvdd v digital input leakage current 0.2 a digital input capacitance 5 pf analogue reference levels adc midrail voltage vmid1c avdd1/2 v adc buffered positive reference voltage vref1c vmid1c v dac midrail voltage vmid2c v ref2vdd/2 v potential divider resistance avdd1 to vmid1c vmid1c to agnd1 100 k ? vref2vdd to vmid2c vmid2c to vref2gnd vmid_sel[1:0] = 01 19 (note 2) k ? analogue line outputs output signal level (0db) -10% 2.0x avdd1/3.3 +10% vrms maximum capacitance load 11 nf minimum resistance load 1 k ? analogue inputs input signal level (0db) 2.0 x avdd1/3.3 vrms input impedance 48 k input capacitance 5 pf dac performance (dac1 to lineout1l/r, dac2 to lineout2l/r) signal to noise ratio 1,5 snr a-weighted @ fs = 48khz 90 100 db a-weighted @ fs = 96khz 100 db a-weighted @ fs = 192khz 100 db dynamic range 2,5 dnr a-weighted, -60db full scale input 90 100 db total harmonic distortion 3,5 thd 1khz, 0dbfs @ fs = 48khz -87 -80 db 1khz, 0dbfs @ fs = 96khz -86 db 1khz, 0dbfs @ fs = 192khz -85 db channel separation 4,5 1khz 110 db channel level matching 0.1 db channel phase deviation 1khz 0.01 degree power supply rejection ratio psrr 1khz, 100mvpp 50 db 20hz to 20khz, 100mvpp 45 db
production data WM8595 w pd, rev 4.2, january 2011 9 test conditions avdd2=9v, avdd1=dvdd=3.3v, agnd1=agnd2=0v, dgnd=0v, t a =+25 ? c, 1khz signal, fs=48khz, mclk=256fs unless otherwise stated parameter symbol test conditions min typ max unit adc performance signal to noise ratio 1,5 snr a-weighted, 0db gain @ fs = 48khz 85 96 db a-weighted, 0db gain @ fs = 96khz 98 db dynamic range 2,5 dnr a-weighted, -60db full scale input 85 96 db total harmonic distortion 3,5 thd 1khz, -1dbfs @ fs = 48khz -80 -70 db 1khz, -1dbfs @ fs = 96khz -78 db channel separation 4,5 1khz 110 db channel level matching 0.1 db channel phase deviation 1khz 0.01 degree power supply rejection ratio psrr 1khz, 100mvpp 70 db 20hz to 20khz, 100mvpp 52 db digital volume control adc minimum digital volume -97 db adc maximum digital volume +30 db adc volume step size 0.5 db dac minimum digital volume -100 db dac maximum digital volume +12 db dac volume step size 0.5 db analogue volume control minimum gain -73.5 db maximum gain +6 db step size 0.5 db mute attenuation 120 db crosstalk dac to adc 1khz signal, adc fs=48khz, dac fs=44.1khz 100 db 20khz signal, adc fs=48khz, dac fs=44.1khz 100 db adc to dac 1khz signal, adc fs=48khz, dac fs=44.1khz 100 db 20khz signal, adc fs=48khz, dac fs=44.1khz 100 db
WM8595 production data w pd, rev 4.2, january 2011 10 terminology 1. signal-to-noise ratio (dbfs) ? snr is the difference in level between a reference full scale output signal and the device output with no signal applied. this ratio is also called idle channel noise. (no auto-zero or automute function is employed in achieving these results). 2. dynamic range (dbfs) ? dnr is a measure of the difference in level between the highest and lowest components of a signal. normally a thd measurement at -60dbfs. the measured signal is then corrected by adding 60db to the result, e.g. thd @ -60dbfs = -30db, dnr = 90db. 3. total harmonic distortion (dbfs) ? thd is the difference in level between a reference full scale output signal and the first seven odd harmonics of the output signal. to calculate the ratio, the fundamental frequency of the output signal is notched out and an rms value of the next seven odd harmonics is calculated. 4. channel separation (db) ? also known as cross-talk. this is a measure of the amount one channel is isolated from the other. normally measured by sending a full scale signal down one channel and measuring the other. 5. all performance measurements carried out with 20khz low pass filter, and where noted an a-weighted filter. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. the low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. notes: 1. all minimum and maximum values are subject to change. 2. this resistance is selectable using vmid_sel[1:0] ? see figure 47 for full details. 3. see p81 for details of extended input impedance configuration.
production data WM8595 w pd, rev 4.2, january 2011 11 master clock timing figure 1 mclk timing test conditions avdd1, dvdd = 3.3v, avdd2 = 9v, agnd1, agnd2, dgnd = 0v, t a = +25 o c parameter symbol min typ max unit master clock timing information mclk system clock cycle time t mclky 27 120 ns mclk duty cycle 40:60 60:40 % mclk period jitter 200 ps mclk rise/fall times 10 ns table 1 master clock timing requirements reset timing figure 2 reset timing test conditions avdd1, dvdd = 3.3v, avdd2 = 9v, agnd1, agnd2, dgnd = 0v, t a = +25 o c parameter symbol min typ max unit reset timing information reset pulsewidth low t reset 10 ns table 2 reset timing requirements
WM8595 production data w pd, rev 4.2, january 2011 12 digital audio interface timing ? slave mode figure 3 slave mode digital audio data timing test conditions avdd1, dvdd = 3.3v, avdd2 = 9v, agnd1, agnd2, dgnd = 0v, t a = +25 ? c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bclk cycle time t bcy 80 ns bclk pulse width high t bch 30 ns bclk pulse width low t bcl 30 ns lrclk set-up time to bclk rising edge t lrsu 22 ns lrclk hold time from bclk rising edge t lrh 25 ns dacdat (input) hold time from lrclk rising edge t dh 25 ns dacdat (input) set-up time to bclk rising edge t ds 25 ns adcdat (output) propagation delay from bclk falling edge t dd 4 16 ns table 3 slave mode audio interface timing
production data WM8595 w pd, rev 4.2, january 2011 13 digital audio interface timing ? master mode figure 4 master mode digital audio data timing test conditions avdd1, dvdd = 3.3v, avdd2 = 9v, agnd1, agnd2, dgnd = 0v, t a = +25 ? c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information lrclk propagation delay from bclk falling edge t dl 4 16 ns adcdat (output) propagation delay from bclk falling edge t dda 4 16 ns dacdat (input) setup time to bclk rising edge t dst 22 ns dacdat (input) hold time to bclk rising edge t dht 25 ns table 4 master mode audio interface timing
WM8595 production data w pd, rev 4.2, january 2011 14 control interface timing ? 2-wire mode figure 5 control interface timing ? 2-wire serial control mode test conditions avdd1, dvdd = 3.3v, avdd2 = 9v, agnd1, agnd2, dgnd = 0v, t a = +25 ? c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk pulse cycle time t scy 2500 ns sclk duty cycle 40/60 60/40 % sclk frequency 400 khz hold time (start condition) t stho 600 ns setup time (start condition) t stsu 600 ns data setup time t dsu 100 ns sda, sclk rise time 300 ns sda, sclk fall time 300 ns setup time (stop condition) t stop 600 ns data hold time t dho 900 ns pulse width of spikes that will be suppressed t ps 2 8 ns table 5 control interface timing ? 2-wire serial control mode
production data WM8595 w pd, rev 4.2, january 2011 15 control interface timing ? 3-wire mode figure 6 control interface timing ? 3-wire serial control mode test conditions avdd1, dvdd = 3.3v, avdd2 = 9v, agnd1, agnd2, dgnd = 0v, t a = +25 ? c, slave mode, fs = 48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to cs rising edge t scs 80 ns sclk pulse cycle time t scy 160 ns sclk duty cycle 40/60 60/40 % sda to sclk set-up time t dsu 20 ns sda hold time from sclk rising edge t dho 40 ns sdout propagation delay from sclk falling edge t dl 5 ns cs pulse width high t csh 40 ns cs falling to sclk rising t css1 40 ns sclk failing to cs rising t css2 40 ns pulse width of spikes that will be suppressed t ps 2 8 ns table 6 control interface timing ? 3-wire serial control mode
WM8595 production data w pd, rev 4.2, january 2011 16 power on reset (por) figure 1 power supply timing requirements test conditions dvdd = 3.3v, avdd1 = 3.3v, avdd2 = 9v dgnd = agnd1 = agnd2 = 0v, t a = +25 o c, t a_max = +125 o c, t a_min = -25 o c avdd1 max = dvdd max = 3.63v, avdd1 min = dvdd mim = 2.97v avdd2 max = 9.9v, avdd2 min = 8.1v parameter symbol test conditions min typ max unit power supply input timing information vdd level to por defined (dvdd rising) v pord measured from dgnd 0.27 0.36 0.60 v vdd level to por rising edge (dvdd rising) v pord_hi measured from dgnd 1.34 1.88 2.32 v vdd level to por falling edge (dvdd falling) v pord_lo measured from dgnd 1.32 1.86 2.30 v vdd level to por rising edge (avdd1 rising) v por1_hi measured from dgnd 1.65 1.68 1.85 v vdd level to por falling edge (avdd1 falling) v por1_lo measured from dgnd 1.63 1.65 1.83 v vdd level to por rising edge (avdd2 rising) v por2_hi measured from dgnd 1.80 1.86 2.04 v vdd level to por falling edge (avdd2 falling) v por2_lo measured from dgnd 1.76 1.8 2.02 v table 7 power on reset
production data WM8595 w pd, rev 4.2, january 2011 17 device description introduction the WM8595 is a high performance multi-channel audio codec with 2vrms line level inputs and outputs and flexible digital input / output switching. the device comprises a 24-bit stereo adc, two 24-bit stereo dacs with independent sampling rates and digital volume control, two stereo pgas in the output path, a flexible digital audio interface multiplexer, a flexible analogue input multiplexer. analogue inputs and outputs are all at 2vrms line level, minimising external component count. the dacs can operate from independent left/right clocks, bit clocks and master clo cks with independent data inputs. alternatively, the dacs can be synchronised to use the same clocks with independent data inputs. the adc uses a separate left/right clock, bit clock and master clock, allowing independent recording and playback in audio applications. the adc audio interface can be configured to operate in either master or slave clocking mode. in master mode, left/right clocks and bit clocks are all outputs. in slave mode, left/right clocks and bit clocks are all inputs. the adc includes digital gain control, allowing signals to be gained and attenuated between +30db and -97db in 0.5db steps. the dacs include independent digital volume control, which is adjustable between +12db and -100 db in 0.5db steps. the dacs can be configured to output stereo audio data and a range of mono audio options. the input analogue multiplexer accepts six stereo line level inputs at up to 2vrms, and allows any stereo input to be routed to the input of the adc. the output pgas have optional zero cross functionality, with gain adjustable between +6db and - 73.5db in 0.5db steps, and configurable soft ramp rate. analogue audio is output at 2vrms line level. the digital audio interface multiplexer allows flexible routing of the digital signals internal to the device between the independent adc, dac1 and dac2 audio interfaces from the digital audio ports. by integrating this functionality into the WM8595, the external component count and board space normally required to switch between various digital audio sources can be significantly reduced. control of the internal functionality of the device is by 2-wire or 3-wire serial control interface with readback. the interface may be asynchronous to the audio data interface as control data will be re- synchronised to the audio processing internally. in addition, control of mute, emergency shutdown and reset may also be achieved by pin control. operation using system clocks of 128fs, 192fs, 256fs, 384fs, 512fs, 768fs or 1152fs is provided. adc and dacs may be clocked independently. sampling rates from 32khz to 192khz are supported for both dacs provided the appropriate master clo cks are i nput. sampling rates from 32khz to 96khz are supported for the adc provided the appropriate master clock is input. the audio data interface supports right justified, left justified, and i2s interface formats along with a highly flexible dsp serial port interface format.
WM8595 production data w pd, rev 4.2, january 2011 18 control interface control of the WM8595 is achieved by a 2-wire sm-bus-compliant or 3-wire spi compliant serial interface with readback. software interface mode is selected using the cifmode pin as shown in table 8 below: cifmode (pin 44) interface format low 2 wire high 3 wire table 8 control interface mode selection 2-wire (sm-bus compatible) serial control interface mode many devices can be controlled by the same bus, and each device has a unique 7-bit address. register write the controller indicates the start of data transfer with a high to low transition on sda while sclk remains high. this indicates that a device address and data will follow. all devices on the 2-wire bus respond to the start condition and shift in the next eight bits on sda (7-bit address and read/write bit, msb first). if the device address received matches the address of the WM8595, the WM8595 responds by pulling sda low on the next clock pulse (ack). if the address is not recognised, the WM8595 returns to the idle condition and waits for a new start condition with valid address. when the WM8595 has acknowledged a correct address, the controller sends the first byte of control data (b23 to b16, i.e. the WM8595 register address). the WM8595 then acknowledges the first data byte by pulling sda low for one sclk pulse. the controller then sends a second byte of control data (b15 to b8, i.e. the first 8 bits of register data), and the WM8595 acknowledges again by pulling sda low for one sclk pulse. finally, the controller sends a third byte of control data (b7 to b0, i.e. the final 8 bits of register data), and the WM8595 acknowledges again by pulling sda low for one sclk pulse. the transfer of data is complete when there is a low to high transition on sda while sclk is high. after receiving a complete address and data sequence the WM8595 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda changes while sclk is high), the WM8595 reverts to the idle condition. the WM8595 device 2-wire write address is 34h (0110100) or 36h (0110110), selectable by control of cs . cs (pin 46) 2-wire bus address (b[7:1]) 0 34h (011010) 1 36h (011011) table 9 2-wire control interface bus address selection figure 7 2-wire write protocol
production data WM8595 w pd, rev 4.2, january 2011 19 auto-increment register write it is possible to write to multiple consecutive registers using the auto-increment feature. when auto_inc is set, the register write protocol follows the method shown in figure 8 . as with normal register writes, the controller indicates the start of data transfer with a high to low transition on sda while sclk remains high, and all devices on the bus receive the device address. when the WM8595 has acknowledged a correct address, the controller sends the first byte of control data (a6 to a0, i.e. the WM8595 initial register address). the WM8595 then acknowledges the first control data byte by pulling sda low for one sclk pulse. the controller then sends a byte of register data. the WM8595 acknowledges the first byte of register data, auto-increments the register address to be written to, and waits for the next byte of register data. subsequent bytes of register data can be written to consecutive registers of the WM8595 without setting up the device and register address. the transfer of data is complete when there is a low to high transition on sda while sclk is high. figure 8 2-wire auto-increment register write register readback the WM8595 allows readback of all registers with data output on the bidirectional sda pin. the protocol is similar to that used to write to the device. the controller will issue the device address followed by a write bit, and the register index will then be passed to the WM8595. at this point the controller will issue a repeated start condition and resend the device address along with a read bit. the WM8595 will acknowledge this and the WM8595 will become a slave transmitter. the WM8595 will place the data from the indexed register onto sda msb first. when the controller receives the first byte of data, it acknowledges it. when the controller receives the second and final byte of data it will not acknowledge receipt of the data indicating that it will resume master transmitter control of sda. the controller will then issue a stop command completing the read cycle. figure 9 2-wire read protocol auto-increment register readback it is possible to read from multiple consecutive registers in continuous readback mode. continuous readback mode is selected by setting auto_inc. in continuous readback mode, the WM8595 will return the indexed register first, followed by consecutive registers in increasing index order until the controller issues a stop sequence. figure 10 2-wire auto-increment register readback
WM8595 production data w pd, rev 4.2, january 2011 20 3-wire (spi compatible) serial control interface mode register write sda is used for the program data, sclk is used to clock in the program data and cs is use to latch in the program data. sda is sampled on the rising edge of sclk. the 3-wire interface write protocol is shown in figure 11. figure 11 3-wire serial interface write protocol ? w indicates write operation. ? a[6:0] is the register index. ? b[15:0] is the data to be written to the register indexed. ? cs is edge sensitive ? the data is latched on the rising edge of /cs. register read-back the read-only status registers can be read back via the sdout pin. read back is enabled when the r/w bit is high. the data can then be read by writing to the appropriate register address, to which the device will respond with data. figure 12 3-wire serial interface readback protocol register reset any write to register r0 (00h) will reset the WM8595. all register bits are reset to their default values.
production data WM8595 w pd, rev 4.2, january 2011 21 device id and revision reading from register r0 returns the device id. reading from register r1 returns the device revision number. register address bit label default description r0 device_id 00h 15:0 device_id [15:0] 10000101 10010101 device id a read of this register will return the device id, 0x8595. r1 revision 01h 7:0 revnum [7:0] n/a device revision a read of this register will return the device revision number. this number is sequentially incremented if the device design is updated. table 10 device id and revision number digital audio data formats the WM8595 supports a range of common audio interface formats: ? i 2 s ? left justified (lj) ? right justified (rj) ? dsp mode a ? dsp mode b all formats send the msb first and support word lengths of 16, 20, 24 and 32 bits, with the exception of 32 bit rj mode, which is not supported. audio data for each stereo channel is time multiplexed with the interface?s left/right clock indicating whether the left or right channel is present. the left/right clock is also used as a timing reference to indicate the beginning or end of the data words. in lj, rj and i 2 s modes, the minimum number of bit clock periods per left/right clock period is two times the selected word length. the left/right clock must be high for a minimum of bit clock periods equivalent to the word length, and low for the same period. for example, for a word length of 24 bits, the left/right clock must be high for a minimum of 24 bit clock periods and low for a minimum of 24 bit clock periods. any mark to space ratio is acceptable for the left/right clock provided these requirements are met. in dsp modes a and b, left and right channels must be time multiplexed and input on dacdat. lrclk is used as a frame synchronisation signal to identify the msb of the first input word. the minimum number of bit clock periods per left/right clock period is two times the selected word length. any mark to space ratio is acceptable for the left/right clock provided the rising edge is correctly positioned.
WM8595 production data w pd, rev 4.2, january 2011 22 i2s mode in i 2 s mode, the msb of input data is sampled on the second rising edge of bit clock following a left/right clock transition. the msb of output data changes on the first falling edge of bit clock following a left/right clock transition, and may be sampled on the next rising edge of bit clock. left/right clocks are low during the left channel audio data samples and high during the right channel audio data samples. figure 13 i2s mode timing left justified (lj) mode in lj mode, the msb of the input data is sampled by the WM8595 on the first rising edge of bit clock following a left/right clock transition. the msb of output data changes on the same falling edge of bit clock as left/right clock and may be sampled on the next rising edge of bit clock. left/right clock is high during the left channel audio data samples and low during the right channel audio data samples. figure 14 lj mode timing
production data WM8595 w pd, rev 4.2, january 2011 23 right justified (rj) mode in rj mode the lsb of input data is sampled on the rising edge of bit clock preceding a left/right clock transition. the lsb of output data changes on the falling edge of bit clock preceding a left/right clock transition, and may be sampled on the next rising edge of bit clock. left/right clock is high during the left channel audio data samples and low during the right channel audio data samples. figure 15 rj mode timing dsp mode a in dsp mode a, the msb of channel 1 left data input is sampled on the second rising edge of bit clock following a left/right clock rising edge. channel 1 right data then follows. the msb of output data changes on the first falling edge of bit clock following a left/right clock transition and may be sampled on the rising edge of bit clock. the right channel data is contiguous with the left channel data. figure 16 dsp mode a timing
WM8595 production data w pd, rev 4.2, january 2011 24 dsp mode b in dsp mode b, the msb of channel 1 left data input is sampled on the first bit clock rising edge following a left/right clock rising edge. channel 1 right data then follows. the msb of output data changes on the same falling edge of bclk as the low to high left/right clock transition and may be sampled on the rising edge of bit clock. the right channel data is contiguous with the left channel data. figure 17 dsp mode b timing digital audio interface control the control of the audio interface formats is achieved by register write. dynamically changing the audio data format may cause erroneous operation and is not recommended. interface timing is such that the input data and left/right clock are sampled on the rising edge of the interface bit clock. output data changes on the falling edge of the interface bit clock. by setting the appropriate bit clock and left/right clock polarity bits, the WM8595 adc and dacs can sample data on the opposite clock edges. the control of audio interface formats and clock polarities is summarised in table 11. register address bit label default description r2 dac1_ctrl1 02h 1:0 dac1_ fmt[1:0] 10 dac1 audio interface format 00 = right justified 01 = left justified 10 = i 2 s 11 = dsp 3:2 dac1_ wl[1:0] 10 dac1 audio interface word length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in right justified mode) 4 dac1_bcp 0 dac1 bclk polarity 0 = dacbclk not inverted - data latched on rising edge of bclk 1 = dacbclk inverted - data latched on falling edge of bclk
production data WM8595 w pd, rev 4.2, january 2011 25 register address bit label default description 5 dac1_lrp 0 dac1 lrclk polarity 0 = daclrclk not inverted 1 = daclrclk inverted r7 dac2_ctrl1 07h 1:0 dac2_ fmt[1:0] 10 dac2 audio interface format 00 = right justified 01 = left justified 10 = i 2 s 11 = dsp 3:2 dac2_ wl[1:0] 10 dac2 audio interface word length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in right justified mode) 4 dac2_bcp 0 dac2 bclk polarity 0 = dacbclk not inverted - data latched on rising edge of bclk 1 = dacbclk inverted - data latched on falling edge of bclk 5 dac2_lrp 0 dac2 lrclk polarity 0 = daclrclk not inverted 1 = daclrclk inverted r13 adc_ctrl1 0dh 1:0 adc_ fmt[1:0] 10 adc audio interface format 00 = right justified 01 = left justified 10 = i 2 s 11 = dsp 3:2 adc_ wl[1:0] 10 adc audio interface word length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in right justified mode) 4 adc_bcp 0 adc bclk polarity 0 = adcbclk not inverted - data latched on rising edge of bclk 1 = adcbclk inverted - data latched on falling edge of bclk 5 adc_lrp 0 adc lrclk polarity 0 = adclrclk not inverted 1 = adclrclk inverted table 11 audio interface control
WM8595 production data w pd, rev 4.2, january 2011 26 digital audio interface digital audio data is transferred to and from the WM8595 via the digital audio interface. the dacs have independent data inputs and master clocks, bit clocks and left/right frame clocks, and operate in both master or slave mode the adc has independent master clock, bit clock and left/right frame clock in addition to its data output, and can operate in both master and slave modes. master mode the adc audio interface requires both a left/right frame clock (adclrclk) and a bit clock (adcbclk). these can be supplied externally (slave mode) or they can be generated internally (master mode). selection of master and slave mode is achieved by setting adc_mstr in adc control register 3. the frequency of adclrclk in master mode is dependent upon the adc master clock frequency and the adc_sr[2:0] bits. the frequency of adcbclk in master mode can be selected by adc_bclkdiv[1:0]. both dac1 and dac2 operate in slave mode only. register address bit label default description r14 adc_ctrl2 0eh 2:0 adc_ sr[2:0] 000 adc mclk:lrclk ratio 000 = auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = reserved 5:3 adc_bclk div[2:0] 000 adc bclk rate 000 = mclk / 4 001 = mclk / 8 010 = 32fs 011 = 64fs 100 = 128fs all other values of adc_bclkdiv[2:0] are reserved r15 adc_ctrl3 0fh 0 adc_ mstr 0 adc master mode select 0 = slave mode, adcbclk and adclrclk are inputs to WM8595 1 = master mode, adcbclk and adclrclk are outputs from WM8595 table 12 adc master mode control
production data WM8595 w pd, rev 4.2, january 2011 27 slave mode in slave mode, the master clock to left/right clock ratio for the adc, dac1 and dac2 can be auto- detected or set manually by register write. register address bit label default description r3 dac1_ctrl2 03h 2:0 dac1_ sr[2:0] 000 dac mclk:lrclk ratio 000 = auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs r8 dac2_ctrl2 08h 2:0 dac2_ sr[2:0] 000 r14 adc_ctrl2 0eh 2:0 adc_ sr[2:0] 000 adc mclk:lrclk ratio 000 = auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = reserved table 13 slave mode mclk to lrclk ratio control
WM8595 production data w pd, rev 4.2, january 2011 28 digital audio data sampling rates in a typical digital audio system there is one central clock source producing a reference clock to which all audio data processing is synchronised. this clock is often referred to as the audio system?s master clock. the WM8595 uses independent master clocks for adc and dacs. the external master clocks can be applied directly to the adcmclk, dacmclk1 and dacmclk2 input pins. in a system where there are a number of possible sources for the reference clock, it is recommended that the clock source with the lowest jitter be used for the master clock to optimise the performance of the WM8595. in slave clocking mode the WM8595 has a master detection circuit that automatically determines the relationship between the master clock frequency (adcmclk, dacmclk1, dacmclk2) and the sampling rate (adclrclk, daclrclk1, daclrclk2), to within +/- 32 system clock periods. the master clocks must be synchronised with the left/right clocks, although the device is tolerant of phase variations or jitter on the master clocks. the adc supports master clock to sampling clock ratios of 256fs to 768fs and sampling rates of 32khz to 96khz, provided the internal signal processing of the adc is programmed to operate at the correct rate. the dacs support master clock to sampling clock ratios of 128fs to 1152fs and sampling rates of 32khz to 192khz, provided the internal signal processing of the dacs is programmed to operate at the correct rate. table 14 shows typical master clock frequencies and sampling rates supported by the WM8595 adc. table 15 shows typical master clock frequencies and sampling rates supported by the WM8595 dacs. sampling rate (adclrclk) master clock frequency (mhz) 256fs 384fs 512fs 768fs 32khz 8.192 12.288 16.384 24.576 44.1khz 11.2896 16.9344 22.5792 33.8688 48khz 12.288 18.432 24.576 36.864 88.2khz 22.5792 33.8688 unavailable unavailable 96khz 24.576 unavailable unavailable unavailable table 14 adc master clock frequency versus sampling rate sampling rate (daclrclk1 daclrclk2) master clock frequency (mhz) 128fs 192fs 256fs 384fs 512fs 768fs 1152fs 32khz unavailable unavailable 8.192 12.288 16.384 24.576 36.864 44.1khz unavailable 8.4672 11.2896 16.9344 22.5792 33.8688 unavailable 48khz unavailable 9.216 12.288 18.432 24.576 36.864 unavailable 88.2khz 11.2896 16.9344 22.5792 33.8688 unavailable unavailable unavailable 96khz 12.288 18.432 24.576 36.864 unavailable unavailable unavailable 176.4khz 22.5792 33.8688 unavailable unavailable unavailable unavailable unavailable 192khz 24.576 36.864 unavailable unavailable unavailable unavailable unavailable table 15 dac master clock frequency versus sampling rate
production data WM8595 w pd, rev 4.2, january 2011 29 dac features the WM8595 includes two 24-bit dacs with independent clocks and independent data inputs. the dacs include digital volume control with zero cross and soft mute, de-emphasis support, and the capability to select the output channels to be stereo or a range of mono options. the dacs are enabled by writing to dac1_en and dac2_en. register address bit label default description r2 dac1_ctrl1 02h 8 dac1_en 0 dac1 enable 0 = dac disabled 1 = dac enabled r7 dac2_ctrl1 07h 8 dac2_en 0 dac2 enable 0 = dac2 disabled 1 = dac2 enabled table 16 dac enable control digital volume control the WM8595 dacs include independent digital volume control, allowing the digital gain to be adjusted between -100db and +12db in 0.5db steps. all four dac channels can be controlled independently. alternatively, global update bits allow the user to write all volume changes before the volume is updated. volume control includes optional zero cross functionality. when zero cross is enabled, volume changes are not applied until the output level crosses vmid. zero cross helps to prevent pop and click noise when changing volume settings. register address bit label default description r5 dac1l_vol 05h 7:0 dac1l _vol[7:0] 11001000 dac digital volume 0000 0000 = -100db 0000 0001 = -99.5db 0000 0010 = -99db ?0.5db steps 1100 1000 = 0db ?0.5db steps 1101 1111 = +11.5db 111x xxxx = +12db r6 dac1r_vol 06h 7:0 dac1r _vol[7:0] r10 dac2l_vol 0ah 7:0 dac2l _vol[7:0] r11 dac2r_vol 0bh 7:0 dac2r _vol[7:0] r5 dac1l_vol 05h 8 dac1l_vu 0 dac digital volume update 0 = latch dac volume setting into register map but do not update volume 1 = latch dac volume setting into register map and update left and right channels simultaneously r6 dac1r_vol 06h 8 dac1r_vu r10 dac2l_vol 0ah 8 dac2l_vu r11 dac2r_vol 0bh 8 dac2r_vu
WM8595 production data w pd, rev 4.2, january 2011 30 register address bit label default description r2 dac1_ctrl1 02h 7 dac1 _zcen 1 dac digital volume control zero cross enable 0 = do not use zero cross 1 = use zero cross r7 dac2_ctrl1 07h 7 dac2 _zcen table 17 dac digital volume control softmute a soft mute can be applied to dac1 and dac2 independently. register address bit label default description r2 dac1_ctrl1 02h 9 dac1_ mute 0 dac softmute 0 = normal operation 1 = softmute applied r7 dac2_ctrl1 07h 9 dac2_ mute 0 table 18 dac softmute control -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 0 0.001 0.002 0.003 0.004 0.005 0.006 time(s) figure 18 application and release of dac soft mute figure 18 shows the applications and release of dac soft mute whilst a full amplitude sinusoid is being played at 48khz sampling rate. when dacx_mute (lower trace) is asserted, the output (upper trace) of the appropriate dac will decay exponentially from the dc level of the last input sample towards vmid2c with a time constant of approximately 64 input samples. when dacx_mute is de-asserted, the output will restart immediately from the current input sample.
production data WM8595 w pd, rev 4.2, january 2011 31 digital monomix control each dac can be independently set to output a range of mono and stereo options. each dac output channel can output left channel data, right channel data or a mix of left and right channel data. register address bit label default description r2 dac1_ctrl1 02h 11:10 dac1_op _mux[1:0] 00 dac1 digital monomix 00 = stereo (normal operation) 01 = mono (left data to dac1r) 10 = mono (right data to dac1l) 11 = digital monomix, (l+r)/2 r7 dac2_ctrl1 07h 11:10 dac2_op _mux[1:0] 00 dac2 digital monomix 00 = stereo (normal operation) 01 = mono (left data to dac2r) 10 = mono (right data to dac2l) 11 = digital monomix, (l+r)/2 table 19 digital monomix control de-emphasis a digital de-emphasis filter may be applied to the dac outputs when the sampling frequency is 44.1khz. the de-emphasis filter for each dac can be applied independently. the de-emphasis filter responses and error can be seen in figure 60 de-emphasis frequency response (32khz) and figure 61 de-emphasis error (32khz). note: de-emphasis is not available when mclk=192fs. register address bit label default description r2 dac1_ctrl1 02h 6 dac1 _deemph 0 dac1 de-emphasis 0 = no de-emphasis 1 = apply 44.1khz de-emphasis r7 dac2_ctrl1 07h 6 dac2 _deemph 0 dac2 de-emphasis 0 = no de-emphasis 1 = apply 44.1khz de-emphasis table 20 de-emphasis control simulataneous dac1 and dac2 control if the same settings are required to both dac1 and dac2, it is possible to have the register settings of dac2 copy the register settings made to dac1. to use this feature, the user must ensure that dac2_copy_dac1 is set before writes are made to dac1. any writes then made to r2-6 are automatically made to r7-11. example (when dac2_copy_dac1=1): register write actual register setting r2 = 0x0001 r2 = 0x0001 & r7 = 0x0001 r3 = 0x0023 r3 = 0x0023 & r8 = 0x0023 r4 = 0x0045 r4 = 0x0045 & r9 = 0x0045 r5 = 0x0067 r5 = 0x0067 & r10 = 0x0067 r6 = 0x0089 r6 = 0x0089 & r11 = 0x0089 register address bit label default description r12 enable 0bh 1 dac2_ copy_ dac1 0 dac2 configuration control 0 = dac2 settings independent of dac1 1 = dac2 settings are the same as dac1 table 21 dac2 configuration control
WM8595 production data w pd, rev 4.2, january 2011 32 analogue output volume control analogue volume control each analogue output includes analogue volume control. volume changes can be applied to each output immediately as they are written. alternatively, all volume changes can be written, and then all volume changes can be applied simultaneously using the volume update feature. volume control includes optional zero cross functionality. when zero cross is enabled, volume changes are not applied until the output level crosses the dc level of the analogue channel (vmid). zero cross helps to prevent pop and click noise when changing volume settings. the zero cross function includes a timeout which forces volume changes if a zero cross event does not occur. the timeout period is a maximum of 278ms. register address bit label default description r19 pga1l_vol 13h 7:0 pga1l_ vol[7:0] 00001100 pga volume 0000 0000 = +6db 0000 0001 = +5.5db ?0.5db steps 00001100 = 0db ? 1001 1110 = -73.5db 1001 1111 = pga mute r20 pga1r_vol 14h 7:0 pga1r_ vol[7:0] r21 pga2l_vol 15h 7:0 pga2l_ vol[7:0] r22 pga2r_vol 16h 7:0 pga2r_ vol[7:0] r19 pga1l_vol 13h 8 pga1l_ vu 0 pga volume update 0 = latch corresponding volume setting into register map but do not update volume 1 = latch corresponding volume setting into register map and update all channels simultaneously r20 pga1r_vol 14h 8 pga1r_ vu r21 pga2l_vol 15h 8 pga2l_ vu r22 pga2r_vol 16h 8 pga2r_ vu r25 pga_ctrl1 19h 2 pga1l_ zc 0 pga gain zero cross enable 0 = pga gain updates occur immediately 1 = pga gain updates occur on zero cross 3 pga1r_ zc 4 pga2l_ zc 5 pga2r_ zc table 22 analogue volume control
production data WM8595 w pd, rev 4.2, january 2011 33 volume ramp analogue volume can be adjusted by step change or by soft ramp. the ramp rate is dependent upon the sampling rate. the sampling rate upon which the volume ramp rate is based can be selected between the dac sampling rate or the adc sampling rate in either slave mode or master mode. the ramp rates for common audio sample rates are shown in table 23: sample rate for pga (khz) divide by pga ramp rate (ms/db) 32 8 0.50 44.1 8 0.36 48 8 0.33 88.2 16 0.36 96 16 0.33 176.4 32 0.36 192 32 0.33 table 23 analogue volume ramp rate for example, when using a sample rate of 48khz, the time taken for a volume change from and initial setting of 0db to -20db is calculated as follows: volume change (db) x pga ramp rate (ms/db) = 20 x 0.33 = 6.6ms when changing from one pga ramp clock source to another, it is recommended that pga_safe_sw is set to 0. this forces the clock switch over to occur at a point where all relevant clock signals are zero, ensuring glitch-free operation. this process can take up to 32 left/right clock cycles. if a faster change in pga ramp rate clock source is required, pga_force can be set to 1. this forces the change in clock source to occur immediately regardless of the state of the relevant clock signals internally. glitch-free operation is not guaranteed under these conditions. pga_force must be set back to 0 to initialise the timing circuits with the new clock. if the volume ramp function is not required when increasing or decreasing volume, this block can be bypassed by setting attack_bypass or decay_bypass to 1. figure 19 shows the effect of these register settings: figure 19 attack_bypass and decay_bypass functionality
WM8595 production data w pd, rev 4.2, january 2011 34 note: when attack_ bypass=1 or decay_bypass=1, it is recomm ended that the zero cross function for the pga is used to eliminate click noise when changing volume settings. register address bit label default description r25 pga_ctrl1 19h 0 decay_ bypass 0 pga gain decay mode 0 = pga gain will ramp down 1 = pga gain will step down 1 attack_ bypass 0 pga gain attack mode 0 = pga gain will ramp up 1 = pga gain will step up r27 add_ctrl1 1bh 6:4 pga_ sr[2:0] 001 sample rate for pga 000 = 32khz 001 = 44.1khz 010 = 48khz 011 = 88.2khz 100 = 96khz 101 = 176.4khz 11x = 192khz see table 23 for further information on pga sample rate versus volume ramp rate. r36 pga_ctrl3 24h 3:1 pga_ sel[2:0] 000 pga ramp control clock source 000 = lrclk1 001 = lrclk2 010 to 110 = reserved 111 = adclrclk (when adc is being used in master mode) 10 pga_upd 0 pga ramp control clock source mux update 0 = do not update pga clock source 1 = update clock source table 24 analogue volume ramp control
production data WM8595 w pd, rev 4.2, january 2011 35 analogue mute control the analogue pgas can be muted independently and are muted by default. alternatively, all mute bits can be set using a master mute bit, mute_all. setting one of these mute bits is equivalent to setting the relevant pgaxx_vol[7:0] register bits to mute as defined in table 22. register address bit label default description r26 pga_ctrl2 1ah 0 mute_ all 0 master pga mute control 0 = unmute all pgas 1 = mute all pgas 1 pga1l_ mute 1 individual pga mute control 0 = unmute pga 1 = mute pga 2 pga1r_ mute 1 3 pga2l_ mute 1 4 pga2r_ mute 1 table 25 analogue mute control pga enable control the pgas are enabled using pgaxx_en bits as described in table 26 register address bit label default description r31 input_ctrl4 1fh 0 pga1l_ en 0 pga enable controls 0 = pga disabled 1 = pga enabled 1 pga1r_ en 2 pga2l_ en 3 pga2r_ en table 26 pga enable control
WM8595 production data w pd, rev 4.2, january 2011 36 adc features the WM8595 features a stereo 24-bit sigma-delta adc, digital volume control with zero cross, a selectable high pass filter to remove dc offsets, and support for both master and slave clocking modes. register address bit label default description r13 adc_ctrl1 0dh 6 adc_en 0 adc enable 0 = adc disabled 1 = adc enabled table 27 adc enable control adc input selector control the adc input switch can be configured to allow any combination of two inputs to be input to the adc. each input switch channel can be controlled independently. the input switch also includes pgas to provide a range of analogue gain settings between 0db and +12db prior to the adc. these pgas can be enabled and disabled independently. figure 20 adc input selector control
production data WM8595 w pd, rev 4.2, january 2011 37 register address bit label default description r30 input_ctrl1 1eh 3:0 adcl_ sel[3:0] 0000 adc input select 0000 = in1l 0001 = in2l 0010 = in3l 0011 = in4l 0100 = in5l 0101 = in6l 0110 = reserved 0111 = reserved 1000 = in1r 1001 = in2r 1010 = in3r 1011 = in4r 1100 = in5r 1101 = in6r 1110 = reserved 1111 = reserved 7:4 adcr_ sel[4:0] 1000 9:8 adc_amp _vol[1:0] 10 adc amplifier gain control 00 = 0db 01 = +3db 10 = +6db 11 = +12db 10 adc_ switch_ en 0 adc input switch control 0 = adc input switches open 1 = adc input switches closed r31 input_ctrl2 1fh 6 adcl_ amp_en 0 adc input amplifier enable controls 0 = amplifier disabled 1 = amplifier enabled 7 adcr_ amp_en 0 table 28 adc input switch control
WM8595 production data w pd, rev 4.2, january 2011 38 digital volume control the adc digital volume can be adjusted between +30db and -97db in 0.5db steps. left and right channels can be controlled independently. volume changes can be applied immediately to each channel, or volume changes can be written to both channels before writing to an update bit in order to change the volume in both channels simultaneously. volume control includes optional zero cross functionality. when zero cross is enabled, volume changes are not applied until the output level crosses the dc level of the adc output. zero cross helps to prevent pop and click noise when changing volume settings. register address bit label default description r16 adcl_vol 10h 7:0 adcl _vol[7:0] 11000011 adc digital volume 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ?0.5db steps 1100 0011 = 0db ?0.5db steps 1111 1110 = +29.5db 1111 1111 = +30db r17 adcr_vol 11h 7:0 adcr _vol[7:0] 11000011 r16 adcl_vol 10h 8 adcl_vu 0 adc digital volume update 0 = latch adc volume setting into register map but do not update volume 1 = latch adc volume setting into register map and update left and right channels simultaneously r17 adcr_vol 11h 8 adcr_vu 0 r13 adc_ctrl1 0dh 13 adc_zc_ en 1 adc digital volume control zero cross enable 0 = do not use zero cross, change volume instantly 1 = use zero cross, change volume when data crosses zero table 29 adc digital volume control
production data WM8595 w pd, rev 4.2, january 2011 39 channel swap and inversion the WM8595 adc input channels can be inverted and swapped in a number of ways to provide maximum flexibility of input path to the adc. the default configuration provides stereo output data with the left and right channel data in the left and right channels. it is possible to swap the left and right channels, invert them independently, or select the same data from both channels. register address bit label default description r13 adc_ctrl1 0dh 7 adc_ lrswap 0 adc left/right swap 0 = normal 1 = swap left channel data into right channel and vice-versa 8 adcr_ inv 0 adcl and adcr output signal inversion 0 = output not inverted 1 = output inverted 9 adcl_ inv 0 11:10 adc_ data_ sel[1:0] 00 adc data output select 00 = left data from adcl, right data from adcr 01 = left data from adcl, right data from adcl 10 = left data from adcr, right data from adcr 11 = left data from adcr, right data from adcl table 30 adc channel swap control high pass filter the WM8595 includes a high pass filter to remove dc offsets. the high pass filter response is shown on page 77. it is possible to disable the high pass filter by writing to adc_hpd. register address bit label default description r13 adc_ctrl1 0dh 12 adc_hpd 0 adc high pass filter disable 0 = high pass filter enabled 1 = high pass filter disabled table 31 high pass filter disable control
WM8595 production data w pd, rev 4.2, january 2011 40 digital routing control the WM8595 includes a highly flexible digital routing multiplexer, allowing independent systems to be directly connected to the WM8595 without the need for glue logic. the WM8595 consists of two digital audio ?ports?, each with four pins, which can be configured to connect to any of the three internal WM8595 systems (adc, dac1 or dac2) or to any other digital audio ports. an additional adc data pin and two gpio pins are available as auxiliary bidirectional data pins. a simplified block diagram of the digital routing is shown in figure 21: figure 21 digital routing block diagram the default configuration of the clocking is as shown in figure 22 below. it is expected that this configuration will satisfy the majority of the use cases for the WM8595, but if it doesn?t it is possible to route the signals differently. see the following pages for details of this setup. figure 22 default clocking configuration
production data WM8595 w pd, rev 4.2, january 2011 41 digital audio port pin configuration the mclk1 pin is defined as an input or an output using mclk1_sel[2:0]. the bclk1 and lrclk1 pins are always defined as inputs or outputs together using wordclk1_sel[2:0]. dacdat1 is always an input. register address bit label default description r37 aif_mux1 25h 3:1 mclk1_ sel[2:0] 000 mclk1 pin function select 000 = input to WM8595 001 = output mclk2 010 to 111 = reserved 6:4 word clk1_ sel[2:0] 000 bclk1 and lrclk1 pins function select 000 = inputs to WM8595 001 = output bclk2 and lrclk2 010 to 110 = reserved 111 = output adcbclk and adcbclk (when adc is master mode) table 32 digital audio port 1 pin configuration the mclk2 pin is defined as an input or an output using mclk2_sel[2:0]. the bclk2 and lrclk2 pins are always defined as inputs or outputs together using wordclk2_sel[2:0]. dacdat2 is always an input. register address bit label default description r38 aif_mux2 26h 3:1 mclk2_ sel[2:0] 001 mclk2 pin function select 000 = output mclk1 001 = input to WM8595 010 to 111 = reserved 6:4 word clk2_ sel[2:0] 001 bclk2 and lrclk2 pins function select 000 = output bclk1 and lrclk1 001 = inputs to WM8595 010 to 110 = reserved 111 = output adcbclk and adcbclk (when adc is master mode) table 33 digital audio port 2 pin configuration
WM8595 production data w pd, rev 4.2, january 2011 42 adc audio interface clock configuration the WM8595 adc has an independent audio interface which can be configured to select the required signals from any of the digital audio ports. the audio interface is not restricted to take each signal from the same digital audio port, although the bclk and lrclk signals are selected together. the mclk is always an input to the adc audio interface is selected using adcmclk_sel[2:0]. the bclk and lrclk are always selected together, and can be either an input to the adc audio interface (when the adc is in slave mode) or an output from the adc audio interface (when the adc is in master mode). bclk and lrclk are selected using adcwordclk_sel[2:0]. register address bit label default description r44 aif_mux5 2ch 3:1 adc mclk_ sel[2:0] 000 adcmclk select 000 = use mclk1 001 = use mclk2 010 to 111 = reserved 6:4 adc word clk_ sel[2:0] 000 adc bclk and lrclk select 000 = use bclk1 and lrclk1 001 = use bclk2 and lrclk2 010 to 110 = reserved 111 = output adcbclk and adcbclk (when adc is master mode) table 34 adc audio interface clock configuration
production data WM8595 w pd, rev 4.2, january 2011 43 dac1 and dac2 audio interface clock configuration both dacs on the WM8595 have independent audio interfaces which can be configured to select the required signals from any of the digital audio ports. the audio interfaces are not restricted to take each signal from the same digital audio ports, although the bclk and lrclk signals are selected together. dac1mclk and dac2mclk are always inputs to the dac1 and dac2 audio interfaces and are selected using dac1mclk_sel[2:0] and dac2mclk_sel[2:0] respectively. dac1bclk and dac1lrclk are always selected together and can are inputs to the dac1 audio interface. dac2bclk and dac2lrclk are always selected together and are inputs to the dac2 audio interface. dac1bclk and dac1lrclk are selected using dac1wordclk_sel[2:0], while dac2bclk and dac2lrclk are selected using dac2wordclk_sel[2:0]. register address bit label default description r42 aif_mux3 2ah 3:1 dac1 mclk_ sel[2:0] 000 dac1 mclk select 000 = use mclk1 001 = use mclk2 010 to 111 = reserved r43 aif_mux4 2bh dac2 mclk_ sel[2:0] 001 dac2 mclk select 000 = use mclk1 001 = use mclk2 010 to 111 = reserved r42 aif_mux3 2ah 6:4 dac1 word clk_ sel[2:0] 000 dac1 bclk and dac lrclk select 000 = use bclk1 and lrclk1 001 = use bclk2 and lrclk2 010 to 110 = reserved 111 = use adcbclk and adcbclk (when adc is master mode) r43 aif_mux4 2bh dac2 word clk_ sel[2:0] 001 dac2 bclk and dac lrclk select 000 = use bclk1 and lrclk1 001 = use bclk2 and lrclk2 010 to 110 = reserved 111 = use adcbclk and adcbclk (when adc is master mode) r42 aif_mux3 2ah 9:7 dac1 din_ sel[2:0] 000 dac1 din select 000 = use dacdat1 001 = use dacdat2 010 to 100 = reserved 101 = use gpio1 110 = use gpio2 111 = reserved r43 aif_mux4 2bh 9:7 dac2 din_ sel[2:0] 001 dac2 din select 000 = use dacdat1 001 = use dacdat2 010 to 100 = reserved 101 = use gpio1 110 = use gpio2 111 = reserved table 35 dac1 and dac2 audio interface clock configuration
WM8595 production data w pd, rev 4.2, january 2011 44 using gpio pins as additional data pins there are two gpio pins, gpio1 and gpio2, which can be used as additional pins to connect to external devices. gpio1 is controlled by gpio1_sel[2:0] and gpio2 by gpio2_sel[2:0]. register address bit label default description r45 aif_mux9 2dh 3:1 gpio1_ sel[2:0] 101 gpio1 pin function select 000 = source dacdat1 001 = source dacdat2 010 = source adcdat 011 to 100 = reserved 101 = input to WM8595 110 = source gpio2 111 = source adc data output table 36 gpio1 audio interface mux configuration register address bit label default description r46 aif_mux10 2eh 3:1 gpio2_ sel[2:0] 000 gpio2 pin function select 000 = source dacdat1 001 = source dacdat2 010 = source adcdat 011 to 100 = reserved 101 = source gpio1 110 = input to WM8595 111 = source adc data output table 37 gpio2 audio interface mux configuration
production data WM8595 w pd, rev 4.2, january 2011 45 update function to prevent clock contention issues during setup of the digital audio interface mux, an update system has been implemented. this allows the registers to be configured as required and the update to be applied with the last register write synchronise the configuration of the digital audio mux. an update can be generated using any of the update bits shown in table 38. register address bit label default description r37 aif_mux1 25h 10 port1_ upd 0 update 0 = latch corresponding settings into register map but do not update 1 = latch corresponding settings into register map and update all simultaneously r38 aif_mux2 26h 10 port2_ upd r42 aif_mux3 2ah 10 dac1_ upd r43 aif_mux4 2bh 10 dac2_ upd r44 aif_mux5 2ch 10 adc_ upd r45 aif_mux6 2dh 10 gpio1_ upd r46 aif_mux7 2eh 10 gpio2_ upd table 38 audio interface mux update bits
WM8595 production data w pd, rev 4.2, january 2011 46 pop and click performance the WM8595 includes a number of features designed to minimise pops and clicks in various phases of operation including power up, power down, changing analogue paths and starting/stopping clocks. in order to ensure optimum performance, the following sequences should be followed. powerup sequence 1. apply power to the WM8595 (see power on reset). 2. set-up initial internal biases: ? soft_st=1 ? fast_en=1 ? pobctrl=1 ? bufio_en=1 3. enable output drivers to allow the ac coupling capacitors at the output stage to be pre- charged to vmid2c: ? voutxl_en=1 ? voutxr_en=1 4. enable vmid2c. highest resistance string selected here for optimum pop reduction: ? vmid_sel=10 5. wait until vmid2c has fully charged. the time is dependent on the capacitor values used to ac-couple the outputs and to decouple vmid2c, and the vmid_sel value chosen. an approximate delay of 6xrcms can be used, where r is the vmid2c resistance (between avdd1 and vmid2c) and c is the decoupling capacitor on vmid2c, although this time should be determined by the customer using the exact application configuration for best results. ? insert delay 6. enable the master bias and vmid2c buffer: ? bias_en=1 7. switch the output drivers to use the master bias instead of the power up (fast) bias: ? pobctrl=0 8. enable all functions (dacs, adc, pgas) required for use. outputs are muted by default so the write order is not important. 9. unmute the pgas and switch vmid2c resistance to mid setting for normal operation: ? pgaxl_mute=0 ? pgaxr_mute=0 ? vmid_sel=01
production data WM8595 w pd, rev 4.2, january 2011 47 powerdown sequence 1. mute all pgas: ? mute_all=1 2. set up biases for power down mode: ? fast_en=1 ? vmid_sel=01 ? bias_en=1 ? bufio_en=1 ? vmidtog=0 ? soft_st=1 3. switch outputs to use fast bias instead of master bias: ? pobctrl=1 4. power down all WM8595 functions (adc, dacs, pgas etc.). the outputs are muted so the write order is not important. 5. power down vmid to allow the analogue outputs to ramp gently to ground in a pop-free manner. ? vmid_sel=00 6. wait until vmid2c has fully discharged. the time taken depends on system capacitance and should be evaluated by the customer in their application. ? insert delay 7. clamp outputs to ground. ? ape_b=0 8. power down outputs. ? voutxl_en=0 ? voutxr_en=0 9. disable remaining bias control bits. ? fast_en=0 ? pobctrl=0 ? bias_en=0 power supplies can now be safely removed from the WM8595 if desired.
WM8595 production data w pd, rev 4.2, january 2011 48 table 39 describes the various bias control bits for power up/down control: register address bit label default description r35 bias 23h 0 pobctrl 0 bias source for output amplifiers 0 = output amplifiers use master bias 1 = output amplifiers use fast bias 1 vmidtog 0 vmid power down characteristic 0 = slow ramp 1 = fast ramp 2 fast_en 0 fast bias enable 0 = fast bias disabled 1 = fast bias enabled 3 bufio_ en 0 vmid buffer enable 0 = vmid buffer disabled 1 = vmid buffer enabled 4 soft_st 1 vmid soft ramp enable 0 = soft ramp disabled 1 = soft ramp enabled 5 bias_en 0 master bias enable 0 = master bias disabled 1 = master bias enabled also powers down vmid1c 7:6 vmid_ sel[1:0] 00 vmid resistor string value selection (vmid2c only) 00 = off (no vmid) 01 = 38k 10 = 127k 11 = 12.5k the selection is the total resistance of the string from vref2vdd to vref2gnd. the vmid1c resistance is fixed at 200k ? . table 39 bias control global enable control the WM8595 includes a number of enable and disable mechanisms to allow the device to be powered on and off in a pop-free manner. a global enable control bit enables the adc, dac and analogue paths. register address bit label default description r12 enable 0ch 0 global_ en 0 device global enable 0 = adc, dac and pga ramp control circuitry disabled 1 = adc, dac and pga ramp control circuitry enabled table 40 global enable control
production data WM8595 w pd, rev 4.2, january 2011 49 emergency power down in the event of sudden power failure in a system, or any other emergency condition, the shutdown pin may be used to power the device down from any state in a controlled m anner. this may be useful in a system where there is no guarantee the power supplies will be available long enough to complete the recommended power down sequence using software writes. when the shutdown is pulled low, the device will mute and then power down the outputs quietly. if the WM8595 is still receiving clocks, the outputs will be softmuted. if the clocks have stopped, the outputs will be muted immediately. figure 23 shows the operation of shutdown and the effect on the outputs of the device: figure 23 shutdown operation it is expected that power is removed from the device before the device is used again, forcing the device to be reset via the por. if this is not the case, the device must be manually reset by the customer (either by a software or hardware reset) once the shutdown is pulled high again.
WM8595 production data w pd, rev 4.2, january 2011 50 register map d e c a d d r he x a d d r n a me 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 he x d e f a ul t 0 0 0 dev ice_id 0x8595 101revision00000000 0x0000 202dac1_ctrl10000 dac1_mutedac1_endac1_zcendac1_deemphdac1_lrpdac1_bcp 0x008a 303dac1_ctrl20000000000000 0x0000 505dac1l_vol0000000dac1l_vu 0x00c8 606dac1r_vol0000000dac1r_vu 0x00c8 707dac2_ctrl10000 dac2_mutedac2_endac2_zcendac2_deemp h dac2_lrp dac2_bcp 0x008a 808dac2_ctrl20000000000 000 0x0000 100adac2l_vol0000000dac2l_vu 0x00c8 110bdac2r_vol0000000dac2r_vu 0x00c8 120cenable 00000000000000 dac2_copy_dac1 global_en 0x0000 13 0d adc_ctrl1 0 0 adc_zc_en adc_hpd adcl_inv adcr_inv adc_lrswap adc_en adc_lrp adc_bcp 0x200a 140eadc_ctrl2000000000 0x0000 150fadc_ctrl300000000000000 adc_mstr0x0000 1610adcl_vol0000000adcl_vu 0x00c3 1711adcr_vol0000000a dcr_vu 0x00c3 1913pga1l_vol0000000pga1l_vu 0x000c 2014pga1r_vol0000000pga1r_vu 0x000c 2115pga2l_vol0000000pga2l_vu 0x000c 2216pga2r_vol0000000pga2r_vu 0x000c 2519pga_ctrl10000000000pga2r_zcpga2l_zcpga1r_zcpga1l_zc a ttack_bypas d ecay_bypas s 0x0000 261apga_ctrl200000000000pga2r_mutepga2l_mutepga1r_mutepga1l_mutemute_all0x007e 271bgen 000000000 auto_inc0000x0048 301einput_ctrl100000 a dc_switch_e n 0x0080 311finput_ctrl200000000 a dcr_am p_e n a dcl_am p_en 0 0 pga2r_en pga2l_en pga1r_en pga1l_en 0x0000 3422output_ctrl00000vout2r_envout2l_envout1r_envout1l_enape_b00vout2r_trivout2l_trivout1r_trivout1l_tri0x0040 3523bias 00000000 bias_ensoft_stbufioenfast_envmidtogpobctrl0x0010 3624pga_ctrl300000pga_upd000000 00x0002 3725aif_mux100000port1_upd000 0 0x0000 3826aif_mux200000port2_upd000 0 0x0092 422aaif_mux300000dac1_upd 0 0x0000 432baif_mux400000dac2_upd 0 0x0092 442caif_mux500000adc_upd 000 0 0x0000 452daif_mux600000gpio1_upd000000 00x000a 462eaif_mux700000gpio2_upd000000 00x000c read: dev ice_id[ 15:0] / writ e: sw_rst revnum [7:0] dac1_op_m ux[1:0] dac1_wl[1:0] dac1_fm t[1:0] da c2 l_ v ol[ 7:0 ] dac1_sr[2:0] da c1l_ v ol[ 7:0 ] dac1r_vol[7:0] dac2_op_m ux[1:0] dac2_wl[1:0] dac2_fm t[1:0] dac2_sr[2:0] adc_data_sel[1:0] adc_wl[1:0] dac2r_vol[7:0] adc_amp_vol[1:0] adcl_vol[7:0] adcr_vol[7:0] pga 1l_ v ol[ 7:0 ] pga1r_vol[7:0] pga 2 l_ v ol[ 7:0 ] pga 2 r_ v ol7:0 ] adc_fm t[ 1:0] adc_bclkdiv[2:0] adc_sr[2:0] wordclk2_sel[2:0] m clk2_sel[2:0] adcr_sel[3:0] adcl_sel[3:0] pga _ sr[ 2 :0 ] dac1din_sel[2:0] dac1wordclk_sel[2:0] dac1m clk_sel[2:0] v m id_ sel[ 1:0 ] pga _ sel[ 2 :0 ] m clk1_ sel[ 2 :0 ] wordclk1_sel[2:0] gpio1_ sel[ 2 :0 ] gpio2_ sel[ 2:0] dac2din_sel[2:0] dac2wordclk_sel[2:0] dac2m clk_sel[2:0] adcwordclk_sel[2:0] adcm clk_sel[2:0]
production data WM8595 w pd, rev 4.2, january 2011 51 figure 24 r0 ? software reset / device id figure 25 r1 ? device revision register r0 (0h) ? software reset / device id register (device_id) bit # 15 14 13 12 11 10 9 8 read device_id[15:8] write sw_rst default 1 0 0 0 0 1 0 1 bit # 7 6 5 4 3 2 1 0 read device_id[7:0] write sw_rst default 1 0 0 1 0 1 0 1 n/a = not applicable (no function implemented) function description deviceid[15:0] device id a read of this register will return the device id. in this case 0x8595. sw_rst software reset a write of any value to this register will generate a software reset. r1 (01h) ? device revision register (revision) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read revnum[7:0] write n/a n/a n/a n/a n/a n/a n/a n/a default - - - - - - - - n/a = not applicable (no function implemented) function description revnum[7:0] device revision a read of this register will return the device revision number. this number is sequentially incremented if the device design is updated.
WM8595 production data w pd, rev 4.2, january 2011 52 figure 26 r2 ? dac1 control register 1 r2 (02h) ? dac control register 1 (dac1_ctrl1) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 dac1_op_mux[1:0] dac1_mute dac1_en write n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac1_zcen dac1_ deemph dac1_lrp dac1_bcp dac1_wl[1:0] dac1_fmt[1:0] write default 1 0 0 0 1 0 1 0 n/a = not applicable (no function implemented) function description dac1_fmt[1:0] dac1 audio interface format 00 = right justified 01 = left justified 10 = i 2 s 11 = dsp dac1_wl[1:0] dac1 audio interface word length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in right justified mode) dac1_bcp dac1 bclk polarity 0 = dacbclk not inverted ? data latched on rising edge of bclk 1 = dacbclk inverted ? data latched on falling edge of bclk dac1_lrp dac1 lrclk polarity 0 = daclrclk not inverted 1 = daclrclk inverted dac1_deemph dac1 deemphasis 0 = no deemphasis 1 = apply 44.1khz deemphasis dac1_zcen dac1 digital volume control zero cross enable 0 = do not use zero cross 1 = use zero cross dac1_en dac1 enable 0 = dac disabled 1 = dac enabled dac1_mute dac1 softmute 0 = normal operation 1 = softmute applied dac1_op_mux[1:0] dac1 digital monomix 00 = stereo (normal operation) 01 = mono (left data to dac1r) 10 = mono (right data to dac1l) 11 = digital monomix, (l+r)/2
production data WM8595 w pd, rev 4.2, january 2011 53 figure 27 r3 ? dac1 control register 2 r5 (05h) ? dac1l digital volume control register (dac1l_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 dac1l_vu write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac1l_vol[7:0] write default 1 1 0 0 1 0 0 0 n/a = not applicable (no function implemented) function description dac1l_vol[7:0] dac1l digital volume 0000 0000 = -100db 0000 0001 = -99.5db 0000 0010 = -99db ?0.5db steps 1100 1000 = 0db ?0.5db steps 1101 1111 = +11.5db 111x xxxx = + 12db dac1l_vu dac1l digital volume update 0 = latch dac1l_vol[7:0] into register map but do not update volume 1 = latch dac1l_vol[7:0] into register map and update left and right channels simultaneously figure 28 r5 ? dac1l digital volume control register r3 (03h) ? dac1 control register 2 (dac1_ctrl2) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 0 dac1_sr[2:0] write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description dac1_sr[2:0] dac1 mclk:lrclk ratio 000 = auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs
WM8595 production data w pd, rev 4.2, january 2011 54 r6 (06h) ? dac1r digital volume control register (dac1r_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 dac1r_vu write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac1r_vol[7:0] write default 1 1 0 0 1 0 0 0 n/a = not applicable (no function implemented) function description dac1r_vol[7:0] dac1r digital volume 0000 0000 = -100db 0000 0001 = -99.5db 0000 0010 = -99db ?0.5db steps 1100 1000 = 0db ?0.5db steps 1101 1111 = +11.5db 111x xxxx = + 12db dac1r_vu dac1r digital volume update 0 = latch dacr_vol[7:0] into register map but do not update volume 1 = latch dacr_vol[7:0] into register map and update left and right channels simultaneously figure 29 r6 ? dac1r digital volume control register
production data WM8595 w pd, rev 4.2, january 2011 55 r7 (07h) ? dac2 control register 1 (dac2_ctrl1) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 dac2_op_mux[1:0] dac2_mute dac2_en write n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac2_zcen dac2_ deemph dac2_lrp dac2_bcp dac2_wl[1:0] dac2_fmt[1:0] write default 1 0 0 0 1 0 1 0 n/a = not applicable (no function implemented) function description dac2_fmt[1:0] dac2 audio interface format 00 = right justified 01 = left justified 10 = i 2 s 11 = dsp dac2_wl[1:0] dac2 audio interface word length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in right justified mode) dac2_bcp dac2 bclk polarity 0 = dacbclk not inverted ? data latched on rising edge of bclk 1 = dacbclk inverted ? data latched on falling edge of bclk dac2_lrp dac2 lrclk polarity 0 = daclrclk not inverted 1 = daclrclk inverted dac2_deemph dac2 deemphasis 0 = no deemphasis 1 = apply 44.1khz deemphasis dac2_zcen dac2 digital volume control zero cross enable 0 = do not use zero cross 1 = use zero cross dac2_en dac2 enable 0 = dac2 disabled 1 = dac2 enabled dac2_mute dac2 softmute 0 = normal operation 1 = softmute applied dac2_op_mux[1:0] dac2 digital monomix 00 = stereo (normal operation) 01 = mono (left data to right dac2) 10 = mono (right data to left dac2) 11 = digital monomix, (l+r)/2 figure 30 r7 ? dac2 control register 1
WM8595 production data w pd, rev 4.2, january 2011 56 r8 (08h) ? dac2 control register 2 (dac2_ctrl2) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 0 dac2_sr[2:0] write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description dac2_sr[2:0] dac2 mclk:lrclk ratio 000 = auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs figure 31 r8 ? dac2 control register 2 r10 (0ah) ? dac2l digital volume control register (dac2l_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 dac2l_vu write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac2l_vol[7:0] write default 1 1 0 0 1 0 0 0 n/a = not applicable (no function implemented) function description dac2l_vol[7:0] dac2 digital volume 0000 0000 = -100db 0000 0001 = -99.5db 0000 0010 = -99db ?0.5db steps 1100 1000 = 0db ?0.5db steps 1101 1111 = +11.5db 111x xxxx = + 12db dac2l_vu dac2 digital volume update 0 = latch dac2l_vol[7:0] into register map but do not update volume 1 = latch dac2l_vol[7:0] into register map and update left and right channels simultaneously figure 32 r10 ? dac2l digital volume control register
production data WM8595 w pd, rev 4.2, january 2011 57 r11 (0bh) ? dac2r digital volume control register (dac2r_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 dac2r_vu write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac2r_vol[7:0] write default 1 1 0 0 1 0 0 0 n/a = not applicable (no function implemented) function description dac2r_vol[7:0] dac2r digital volume 0000 0000 = -100db 0000 0001 = -99.5db 0000 0010 = -99db ?0.5db steps 1100 1000 = 0db ?0.5db steps 1101 1111 = +11.5db 111x xxxx = + 12db dac2r_vu dac2r digital volume update 0 = latch dac2r_vol[7:0] into register map but do not update volume 1 = latch dac2r_vol[7:0] into register map and update left and right channels simultaneously figure 33 r11 ? dac2r digital volume control register r12 (0ch) ? device enable register (enable) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 dac2_ copy_dac1 global_en write n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description global_en device global enable 0 = adc, dac and pga ramp control circuitry disabled 1 = adc, dac and pga ramp control circuitry enabled dac2_copy_dac1 dac2 configuration control 0 = dac2 settings independent of dac1 1 = dac2 settings are the same as dac1 figure 34 r12 ? device enable register
WM8595 production data w pd, rev 4.2, january 2011 58 r13 (0dh) ? adc control register 1 (adc_ctrl1) bit # 15 14 13 12 11 10 9 8 read 0 0 adc_zcen adc_hpd adc_data_sel[1:0] adcl_inv adcr_inv write n/a n/a default 0 0 1 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read adc_ lrswap adc_en adc_lrp adc_bcp adc_wl[1:0] adc_fmt[1:0] write default 0 0 0 0 1 0 1 0 n/a = not applicable (no function implemented) function description adc_fmt[1:0] adc audio interface format 00 = right justified 01 = left justified 10 = i 2 s 11 = dsp adc_wl[1:0] adc audio interface word length 00 = 16-bit 01 = 20-bit 10 = 24-bit 11 = 32-bit (not available in right justified mode) adc_bcp adc bclk polarity 0 = adcbclk not inverted ? data latched on rising edge of bclk 1 = adcbclk inverted ? data latched on falling edge of bclk adc_lrp adc lrclk polarity 0 = adclrclk not inverted 1 = adclrclk inverted adc_en adc enable 0 = adc disabled 1 = adc enabled adc_lrswap adc left/right swap 0 = normal 1 = swap left channel data into right channel and vice-versa adcr_inv adcl_inv adcl and adcr output signal inversion 0 = output not inverted 1 = output inverted adc_data_sel[1:0] adc data output select 00 = left data from adcl, right data from adcr (normal stereo) 01 = left data from adcl, right data from adcl (mono left) 10 = left data from adcr, right data from adcr (mono right) 11 = left data from adcr, right data from adcl (reverse stereo) adc_hpd adc high pass filter disable 0 = high pass filter enabled 1 = high pass filter disabled adc_zc_en adc digital volume control zero cross enable 0 = do not use zero cross, change volume instantly 1 = use zero cross, change volume when data crosses zero figure 35 r13 ? adc control register 1
production data WM8595 w pd, rev 4.2, january 2011 59 r14 (0eh) ? adc control register 2 (adc_ctrl2) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 adc_bclkdiv[2:0] adc_sr[2:0] write n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description adc_sr[2:0] adc mclk:lrclk ratio 000 = auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = reserved adc_bclkdiv[2:0] adc bclk rate (when adc in master mode) 000 = mclk / 4 001 = mclk / 8 010 = 32fs 011 = 64fs 100 = 128fs all other values of adc_bclkdiv[2:0] are reserved figure 36 r14 ? adc control register 2 r15 (0fh) ? adc control register 3 (adc_ctrl3) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 0 0 0 adc_mstr write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description adc_mstr adc master mode select 0 = slave mode, adcbclk and adclrclk are inputs to WM8595 1 = master mode, adcbclk and adclrclk are outputs from WM8595 figure 37 r15 ? adc control register 3
WM8595 production data w pd, rev 4.2, january 2011 60 r16 (10h) ? left adc digital volume control register (adcl_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 adcl_vu write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read adcl_vol[7:0] write default 1 1 0 0 0 0 1 1 n/a = not applicable (no function implemented) function description adcl_vol[7:0] left adc digital volume 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ?0.5db steps 1100 0011 = 0db ?0.5db steps 1111 1110 = +29.5db 1111 1111 = +30db adcl_vu left dac digital volume update 0 = latch adcl_vol[7:0] into register map but do not update volume 1 = latch adcl_vol[7:0] into register map and update left and right channels simultaneously figure 38 r16 ? left adc digital volume control register r17 (11h) ? right adc digital volume control register (adcr_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 adcr_vu write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read adcr_vol[7:0] write default 1 1 0 0 0 0 1 1 n/a = not applicable (no function implemented) function description adcr_vol[7:0] right adc digital volume 0000 0000 = digital mute 0000 0001 = -97db 0000 0010 = -96.5db ?0.5db steps 1100 0011 = 0db ?0.5db steps 1111 1110 = +29.5db 1111 1111 = +30db adcr_vu right adc digital volume update 0 = latch adcr_vol[7:0] into register map but do not update volume 1 = latch adcr_vol[7:0] into register map and update left and right channels simultaneously figure 39 r17 ? right adc digital volume control register
production data WM8595 w pd, rev 4.2, january 2011 61 r19 (13h) ? pga1l volume control register (pga1l_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a pga1l_vu default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read pga1l_vol[7:0] write default 0 0 0 0 1 1 0 0 n/a = not applicable (no function implemented) r20 (14h) ? pga1r volume control register (pga1r_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a pga1r_vu default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read pga1r_vol[7:0] write default 0 0 0 0 1 1 0 0 n/a = not applicable (no function implemented) r21 (15h) ? pga2l volume control register (pga2l_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a pga2l_vu default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read pga2l_vol[7:0] write default 0 0 0 0 1 1 0 0 n/a = not applicable (no function implemented) r22 (16h) ? pga2r volume control register (pga2r_vol) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a pga2r_vu default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read pga2r_vol[7:0] write default 0 0 0 0 1 1 0 0 n/a = not applicable (no function implemented) ?continued on next page
WM8595 production data w pd, rev 4.2, january 2011 62 function description pga1l_vol[7:0] pga1r_vol[7:0] pga2l_vol[7:0] pga2r_vol[7:0] input pga volume 0000 0000 = +6db 0000 0001 = +5.5db ?0.5db steps 00001100 = 0db ? 1001 1110 = -73.5db 1001 1111 = pga mute pga1l_vu pga1r_vu pga2l_vu pga2r_vu input pga volume update 0 = latch corresponding volume setting into register map but do not update volume 1 = latch corresponding volume setting into register map and update all channels simultaneously figure 40 r19-24 ? pga volume control registers r25 (19h) ? pga control register 1 (pga_ctrl1) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 pga2r_zc pga2l_zc pga1r_zc pga1l_zc attack_ bypass decay_ bypass write n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description decay_bypass pga gain decay mode 0 = pga gain will ramp down 1 = pga gain will step down attack_bypass pga gain attack mode 0 = pga gain will ramp up 1 = pga gain will step up pga1l_zc pga1r_zc pga2l_zc pga2r_zc pga gain zero cross enable 0 = pga gain updates occur immediately 1 = pga gain updates occur on zero cross zero cross must be disabled to use gain ramp figure 41 r25 ? pga control register 1
production data WM8595 w pd, rev 4.2, january 2011 63 r26 (1ah) ? pga control register 2 (pga_ctrl2) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 pga2r_ mute pga2l_ mute pga1r_ mute pga1l_ mute mute_all write n/a n/a n/a default 0 1 1 1 1 1 1 0 n/a = not applicable (no function implemented) function description mute_all master pga mute control 0 = unmute all output drivers 1 = mute all output drivers pga1l_mute pga1r_mute pga2l_mute pga2r_mute individual pga mute control 0 = unmute output driver 1 = mute output driver figure 42 r26 ? pga control register 2 r27 (1bh) ? additional control register 1 (add_ctrl1) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 pga_sr[2:0] auto_inc 0 0 0 write n/a n/a n/a n/a default 0 1 0 0 1 0 0 0 n/a = not applicable (no function implemented) function description auto_inc 2-wire software mode auto increment enable 0 = auto increment disabled 1 = auto increment enabled pga_sr[2:0] sample rate for pga 000 = 32khz 001 = 44.1khz 010 = 48khz 011 = 88.2khz 100 = 96khz 101 = 176.4khz 11x = 192khz see table 23 for further information on pga sample rate versus volume ramp rate. figure 43 r27 ? additional control register 1
WM8595 production data w pd, rev 4.2, january 2011 64 r30 (1eh) ? input control register 1 (input_ctrl1) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 adc_ switch_en adc_amp_vol[1:0] write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 1 0 bit # 7 6 5 4 3 2 1 0 read adcr_sel[3:0] adcl_sel[3:0] write default 1 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description adcl_sel[3:0] adcr_sel[3:0] adc input select 0000 = in1l 0001 = in2l 0010 = in3l 0011 = in4l 0100 = in5l 0101 = in6l 0110 = reserved 0111 = reserved 1000 = in1r 1001 = in2r 1010 = in3r 1011 = in4r 1100 = in5r 1101 = in6r 1110 = reserved 1111 = reserved adc_amp_vol[1:0] adc amplifier gain control 00 = 0db 01 = +3db 10 = +6db 11 = +12db adc_switch_en adc input switch control 0 = adc input switches open 1 = adc input switches closed figure 44 r30 ? input control register 1
production data WM8595 w pd, rev 4.2, january 2011 65 r31 (1fh) ? input control register 2 (input_ctrl2) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read adcr_amp_ en adcl_amp_ en 0 0 pga2r_en pga2l_en pga1r_en pga1l_en write n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description pga1l_en pga1r_en pga2l_en pga2r_en input pga enable controls 0 = pga disabled 1 = pga enabled adcl_amp_en adcr_amp_en adc input amplifier enable controls 0 = amplifier disabled 1 = amplifier enabled figure 45 r31 ? input control register 2 r34 (22h) ? output control register 3 (output_ctrl) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 vout2r_en vout2l_en vout1r_en write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read vout1l_en ape_b 0 0 vout2r_tri vout2l_tri vout1r_tri vout1l_tri write n/a n/a default 0 1 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description vout1l_tri vout1r_tri vout2l_tri vout2r_tri output amplifier tristate control 0 = normal operation 1 = output amplifier tristate enable (hi-z) ape_b clamp outputs to ground 0 = clamp active 1 = clamp not active vout1l_en vout1r_en vout2l_en vout2r_en output amplifier enables 0 = output amplifier disabled 1 = output amplifier enabled figure 46 r34 ? output control register
WM8595 production data w pd, rev 4.2, january 2011 66 r35 (23h) ? bias control register (bias) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 0 0 0 write n/a n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read vmid_sel[1:0] bias_en soft_st bufio_en fast_en vmidtog pobctrl write default 0 0 0 1 0 0 0 0 n/a = not applicable (no function implemented) function description pobctrl bias source for output amplifiers 0 = output amplifiers use master bias 1 = output amplifiers use fast bias vmidtog vmid power down characteristic 0 = slow ramp 1 = fast ramp fast_en fast bias enable 0 = fast bias disabled 1 = fast bias enabled bufio_en vmid buffer enable 0 = vmid buffer disabled 1 = vmid buffer enabled soft_st vmid soft ramp enable 0 = soft ramp disabled 1 = soft ramp enabled bias_en master bias enable 0 = master bias disabled 1 = master bias enabled also powers down vmid1c vmid_sel[1:0] vmid resistor string value selection (vmid2c only) 00 = off (no vmid) 01 = 38k 10 = 127k 11 = 12.5k the selection is the total resistance of the string from vref2vdd to vref2gnd. the vmid1c resistance is fixed at 200k. figure 47 r35 ? bias control register
production data WM8595 w pd, rev 4.2, january 2011 67 r36 (24h) ? pga control register 3 (pga_ctrl) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 pga_upd 0 0 write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 pga_sel[2:0] 0 write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 1 0 n/a = not applicable (no function implemented) function description pga_sel[2:0] pga ramp control clock source 000 = lrclk1 001 = lrclk2 010 to 110 = reserved 111 = adclrclk (when adc is being used in master mode) pga_upd pga ramp control clock source mux update 0 = do not update pga clock source 1 = update clock source figure 48 r36 ? pga control register
WM8595 production data w pd, rev 4.2, january 2011 68 r37 (25h) ? audio interface mux configuration register 1 (aif_mux1) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 port1_upd 0 0 write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 wordclk1_sel[2:0] mclk1_sel[2:0] 0 write n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description mclk1_sel[2:0] mclk1 pin function select 000 = input to WM8595 001 = output mclk2 010 to 111 = reserved wordclk1_sel[2:0] bclk1 and lrclk1 pins function select 000 = inputs to WM8595 001 = output bclk2 and lrclk2 010 to 110 = reserved 111 = output adcbclk and adcbclk (when adc is master mode) port1_upd port 1 update 0 = latch corresponding port 1 settings into register map but do not update 1 = latch corresponding port 1 settings into register map and update all simultaneously figure 49 r37 ? audio interface mux configuration register 1
production data WM8595 w pd, rev 4.2, january 2011 69 r38 (26h) ? audio interface mux configuration register 2 (aif_mux2) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 port2_upd 0 0 write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 wordclk2_sel[2:0] mclk2_sel[2:0] 0 write n/a n/a default 1 0 0 1 0 0 1 0 n/a = not applicable (no function implemented) function description mclk2_sel[2:0] mclk2 pin function select 000 = output mclk1 001 = input to WM8595 010 = output mclk3 011 = output mclk4 100 = output mclk5 101 to 111 = reserved wordclk2_sel[2:0] bclk2 and lrclk2 pins function select 000 = output bclk1 and lrclk1 001 = inputs to WM8595 010 = output bclk3 and lrclk3 011 = output bclk4 and lrclk4 100 = output bclk5 and lrclk5 101 = output dac1bclk and dac1lrclk (when dac1 is in master mode) 110 = output dac2bclk and dac2lrclk (when dac2 is in master mode) 111 = output adcbclk and adcbclk (when adc is master mode) port2_upd port 2 update 0 = latch corresponding port 2 settings into register map but do not update 1 = latch corresponding port 2 settings into register map and update all simultaneously figure 50 r38 ? audio interface mux configuration register 2
WM8595 production data w pd, rev 4.2, january 2011 70 r42 (2ah) ? audio interface mux configuration register 3 (aif_mux3) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 dac1_upd dac1din_sel[2:1] write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac1din_ sel[0] dac1wordclk_sel[2:0] dac1mclk_sel[2:0] 0 write n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description dac1mclk_sel[2:0] dac1mclk select 000 = use mclk1 001 = use mclk2 010 to 111 = reserved dac1wordclk_ sel[2:0] dac1bclk and dac1lrclk select 000 = use bclk1 and lrclk1 001 = use bclk2 and lrclk2 010 to 110 = reserved 111 = use adcbclk and adcbclk (when adc is master mode) dac1din_sel[2:0] dac1din select 000 = use dacdat1 001 = use dacdat2 010 to 100 = reserved 101 = use gpio1 110 = use gpio2 111 = reserved dac1_upd dac1 clock update 0 = latch corresponding dac1 clock settings into register map but do not update 1 = latch corresponding dac1 clock settings into register map and update all simultaneously figure 51 r42 ? audio interface mux configuration register 3
production data WM8595 w pd, rev 4.2, january 2011 71 r43 (2bh) ? audio interface mux configuration register 4 (aif_mux4) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 dac2_upd dac2din_sel[2:1] write n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read dac2din_ sel[0] dac2wordclk_sel[2:0] dac2mclk_sel[2:0] 0 write n/a default 1 0 0 1 0 0 1 0 n/a = not applicable (no function implemented) function description dac2mclk_sel[2:0] dac2mclk select 000 = use mclk1 001 = use mclk2 010 to 111 = reserved dac2wordclk_ sel[2:0] dac2bclk and dac2lrclk select 000 = use bclk1 and lrclk1 001 = use bclk2 and lrclk2 010 to 110 = reserved 111 = use adcbclk and adcbclk (when adc is master mode) dac2din_sel[2:0] dac2din select 000 = use dacdat1 001 = use dacdat2 010 to 100 = reserved 101 = use gpio1 110 = use gpio2 111 = reserved dac2_upd dac2 clock update 0 = latch corresponding dac2 clock settings into register map but do not update 1 = latch corresponding dac2 clock settings into register map and update all simultaneously figure 52 r43 ? audio interface mux configuration register 4
WM8595 production data w pd, rev 4.2, january 2011 72 r44 (2ch) ? audio interface mux configuration register 5 (aif_mux5) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 adc_upd 0 0 write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 adcwordclk_sel[2:0] adcmclk_sel[2:0] 0 write n/a n/a default 0 0 0 0 0 0 0 0 n/a = not applicable (no function implemented) function description adcmclk_sel[2:0] adcmclk select 000 = use mclk1 001 = use mclk2 010 to 111 = reserved adcwordclk_ sel[2:0] adcbclk and adclrclk select 000 = use bclk1 and lrclk1 001 = use bclk2 and lrclk2 010 to 110 = reserved 111 = output adcbclk and adcbclk (when adc is master mode) adc_upd adc clock update 0 = latch corresponding adc clock settings into register map but do not update 1 = latch corresponding adc clock settings into register map and update all simultaneously figure 53 r44 ? audio interface mux configuration register 5
production data WM8595 w pd, rev 4.2, january 2011 73 r45 (2dh) ? audio interface mux configuration register 6 (aif_mux6) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 gpio1_upd 0 0 write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 gpio1_sel[2:0] 0 write n/a n/a n/a n/a n/a default 0 0 0 0 1 0 1 0 n/a = not applicable (no function implemented) function description gpio1_sel[2:0] gpio1 pin function select 000 = source dacdat1 001 = source dacdat2 010 = source adcdat 011 to 100 = reserved 101 = input to WM8595 110 = source gpio2 111 = source adc data output gpio1_upd gpio1 update 0 = latch corresponding gpio1 settings into register map but do not update 1 = latch corresponding gpio1 settings into register map and update figure 54 r45 ? audio interface mux configuration register 6 r46 (2eh) ? audio interface mux configuration register 7 (aif_mux7) bit # 15 14 13 12 11 10 9 8 read 0 0 0 0 0 gpio2_upd 0 0 write n/a n/a n/a n/a n/a n/a n/a default 0 0 0 0 0 0 0 0 bit # 7 6 5 4 3 2 1 0 read 0 0 0 0 gpio2_sel[2:0] 0 write n/a n/a n/a n/a n/a default 0 0 0 0 1 1 0 0 n/a = not applicable (no function implemented) function description gpio2_sel[2:0] gpio2 pin function select 000 = source dacdat1 001 = source dacdat2 010 = source adcdat 011 to 100 = reserved 101 = source gpio1 110 = input to WM8595 111 = source adc data output gpio2_upd gpio2 update 0 = latch corresponding gpio2 settings into register map but do not update 1 = latch corresponding gpio2 settings into register map and update all simultaneously figure 55 r46 ? audio interface mux configuration register 7
WM8595 production data w pd, rev 4.2, january 2011 74 digital filter characteristics parameter test conditions min typ max unit adc filter passband 0.05db 0.454fs passband ripple 0.05 db stopband 0.546fs stopband attenuation -60 db group delay 16 fs dac filter ? 32khz to 96khz passband 0.1db 0.454fs passband ripple 0.1 db stopband 0.546fs stopband attenuation f > 0.546fs -50 db group delay 10 fs dac filter ? 176.4khz to 192khz passband 0.1db 0.247fs passband ripple 0.1 db stopband 0.753fs stopband attenuation f > 0.546fs -50 db group delay 10 fs
production data WM8595 w pd, rev 4.2, january 2011 75 dac filter responses -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) response (db) figure 56 dac digital filter frequency response ? 44.1, 48 and 96khz figure 57 dac digital filter ripple ?44.1, 48 and 96khz -100 -80 -60 -40 -20 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 frequency (fs) response (db) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) response (db) figure 58 dac digital filter frequency response ? 192khz figure 59 dac digital filter ripple ? 192khz
WM8595 production data w pd, rev 4.2, january 2011 76 digital de-emphasis characteristics -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 0 2 4 6 8 10 12 14 16 response (db) frequency (khz) figure 60 de-emphasis frequency response (32khz) figure 61 de-emphasis error (32khz) figure 62 de-emphasis frequency response (44.1khz) figure 63 de-emphasis error (44.1khz) -10 -8 -6 -4 -2 0 0 5 10 15 20 response (db) frequency (khz) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 response (db) frequency (khz) figure 64 de-emphasis frequency response (48khz) figure 65 de-emphasis error (48khz)
production data WM8595 w pd, rev 4.2, january 2011 77 adc filter responses magnitude (db) up to fs -140 -120 -100 -80 -60 -40 -20 0 20 0.00 0.25 0.50 0.75 frequency magnitude (db): passband ripple -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 0.1 0.00 0.25 frequency figure 66 adc digital filter frequency response figure 67 adc digital filter ripple adc high pass filter the WM8595 has a selectable digital high pass filter to remove dc offsets. the filter response is characterised by the following polynomial. ma gnitude( db) 0 2 4 6 8 101214161820 -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 figure 68 adc highpass filter response 1 - z -1 1 - 0.9995z -1 h(z) =
WM8595 production data w pd, rev 4.2, january 2011 78 applications information recommended external components avdd1 avdd2 dvdd shutdown mute reset cifmode cs sclk sda sdout gpio1 gpio2 mclk1 lrclk1 bclk1 dacdat1 mclk2 lrclk2 bclk2 dacdat2 adcdat in1l in1r in2l in2r in3l in3r in4l in4r in5l in5r in6l in6r agnd1 agnd2 dgnd control interface digital audio interface ac-coupled inputs analogue +3.3v c1 4.7f c2 4.7f c3 4.7f vref1c c4 4.7f vref1gnd vmid1c c5 4.7f vref2vdd c6 4.7f vref2gnd vmid2c c7 4.7f analogue +9v digital +3.3v analogue +3.3v gnd gnd gnd gnd lineout1l lineout1r lineout2l lineout2r ac-coupled outputs 42 18 11 15 16 17 44 46 47 48 45 1 2 4 5 6 7 8 9 10 13 14 24 25 26 27 28 29 30 31 32 33 34 35 43 19 12 36 38 37 39 41 40 23 22 21 20 notes: 1. agnd and dgnd should ideally share a continuous ground plane. where this is not possible, it is recommended that agnd and dgnd are connected as close to the WM8595 as possible. 2. decoupling capacitors shown are very low-esr, multilayer ceramic capacitors and should be placed as near to the WM8595 as possible. equally good audio performance may be obtained using 0.1 f ceramic capacitors near to the WM8595, with a 10 f electrolytic capacitor nearby. note that power up time is a function of the vmid2c resistor string setting and the decoupling capacitor c7. 3. the exposed paddle on the bottom of the qfn package should be connected to agnd
production data WM8595 w pd, rev 4.2, january 2011 79 recommended analogue low pass filter figure 69 recommended analogue low pass filter (shown for vout1l/r) note: see wan0176 for ac coupling capacitor selection information. an external single pole rc filter is recommended (see figure 69) if the device is driving a wideband amplifier. other filter architectures may provide equally good results. relevant application notes the following application notes, available from www.wolfsonmicro.com , may provide additional guidance for the use of the WM8595. device performance: wan0129 ? decoupling and layout methodology for wolfson dacs, adcs and codecs wan0144 ? using wolfson audio dacs and codecs with noisy supplies wan0176 ? ac coupling capacitor selection general: wan0108 ? moisture sensitivity classification and plastic ic packaging wan0109 ? esd damage in integrated circuits: causes and prevention wan0158 ? lead-free solder profiles for lead-free components
WM8595 production data w pd, rev 4.2, january 2011 80 package dimensions dm079.a fl: 48 pin qfn plastic package 7 x 7 x 0.75 mm body, 0.50 mm lead pitch index area (d/2 x e/2) top view c aaa 2 x e2 e2/2 d2 24 l d2/2 c aaa 2 x 25 36 37 48 1 12 13 d e e pin 1 a a1 symbols dimensions (mm) min nom max note a b d d2 e e2 e l 0.75 0.30 0.25 0.20 7.00 bsc 5.75 5.65 5.55 7.00 bsc 0.5 bsc 5.65 5.75 5.55 0.35 0.4 0.45 1 a1 a3 0 0.035 0.05 0.203 ref notes: 1. dimension b applied to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. all dimensions are in millimetres 3. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-002. 4. coplanarity applies to the exposed heat sink slug as well as the terminals. 5. this drawing is subject to change without notice. 6. refer to applications note wan_0118 for further information. jedec, mo-220 tolerances of form and position aaa bbb ccc 0.10 0.08 0.10 ref exposed gnd paddle 6 0.7 0.8 a2 - 0.55 0.57 a2 c ccc b c bbb (a3) c seating plane
production data WM8595 w pd, rev 4.2, january 2011 81 important notice wolfson microelectronics plc (?wolfson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at the date of shipment. wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless required by law or regulation. in order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. wolfson is not liable for applications assistance or customer product design. the customer is solely responsible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM8595 production data w pd, rev 4.2, january 2011 82 revision history date rev originator changes 19/01/10 4.2 ct updated figure 3 slave mode digital timing diagram to latest format. p12. updated table 3 specifications to match figure 3. p12.

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